From bbed40ccc5f37e98f396f8cfcc658112d5f9bc41 Mon Sep 17 00:00:00 2001 From: andrewc Date: Thu, 12 Jan 2023 14:39:25 +1000 Subject: [PATCH] Added CI files and readme --- .gitlab-ci.yml | 122 +++++++++++++++++++++++++++++ README.md | 42 ++++++++++ default.kibot.yaml | 190 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 354 insertions(+) create mode 100644 .gitlab-ci.yml create mode 100644 README.md create mode 100644 default.kibot.yaml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml new file mode 100644 index 0000000..8688f78 --- /dev/null +++ b/.gitlab-ci.yml @@ -0,0 +1,122 @@ +workflow: + rules: + - if: $CI_PIPELINE_SOURCE == "merge_request_event" + - if: $CI_COMMIT_BRANCH && $CI_OPEN_MERGE_REQUESTS + when: never + - if: $CI_COMMIT_BRANCH + +stages: + - run_erc + - run_drc + - gen_mech + - mech_out + - gen_fab + - fab_out + +image: + name: ghcr.io/inti-cmnb/kicad6_auto:1.3.0 + +.main_rules: + rules: + - if: '$CI_PIPELINE_SOURCE == "merge_request_event" && $CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "main"' + - if: $CI_COMMIT_BRANCH == "main" + +.dev_rules: + rules: + - if: '$CI_PIPELINE_SOURCE == "merge_request_event" && $CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "dev"' + - if: $CI_COMMIT_BRANCH == "dev" + +.template: + rules: + - !reference [.main_rules, rules] + variables: + COMMAND: kibot -e "$SCHEM" -c ../default.kibot.yaml -d "../Fabrication/$DIR" -s + SUFFIX: "" + script: + - cd "$DIR" + - echo $COMMAND $SUFFIX | bash + dependencies: [] + parallel: + matrix: + - DIR: '.' + SCHEM: 'proj.kicad_sch' + +.tempout: + extends: .template + artifacts: + when: always + expire_in: 2 mins + paths: + - Fabrication/ + +.temprc: + extends: .template + rules: + - !reference [.main_rules, rules] + - !reference [.dev_rules, rules] + +.tempcoll: + rules: + - !reference [.main_rules, rules] + script: + - ls Fabrication/ + artifacts: + when: always + paths: + - Fabrication/ + +erc: + extends: .temprc + stage: run_erc + variables: + SUFFIX: update_xml,run_drc -i + +drc: + extends: .temprc + stage: run_drc + variables: + SUFFIX: update_xml,run_erc -i + +cad_outputs: + extends: .tempout + rules: + - !reference [.main_rules, rules] + - !reference [.dev_rules, rules] + stage: gen_mech + variables: + SUFFIX: run_drc step + +mech_outputs: + extends: .tempcoll + rules: + - !reference [.main_rules, rules] + - !reference [.dev_rules, rules] + stage: mech_out + dependencies: + - cad_outputs + +sch_outputs: + extends: .tempout + stage: gen_fab + variables: + SUFFIX: run_drc,run_erc print_sch + +pcb_outputs: + extends: .tempout + stage: gen_fab + variables: + SUFFIX: all print_front JLCPCB_fab assembly step + +bom: + extends: .tempout + stage: gen_fab + variables: + SUFFIX: all bom + +fab_outputs: + extends: .tempcoll + stage: fab_out + dependencies: + - sch_outputs + - pcb_outputs + - bom diff --git a/README.md b/README.md new file mode 100644 index 0000000..c624881 --- /dev/null +++ b/README.md @@ -0,0 +1,42 @@ +# Dependencies +- [Kicad 6](https://www.kicad.org/) +- [git-lfs](https://git-lfs.com/) + +# Setup +1. Fork or clone and change origin remote-url. +2. Checkout dev (branch off dev if desired) +2. Rename/move files to match project name (make sure to update for [CI](#CI) too) +3. Lock the file you want to edit, see [Locking](#Locking) +4. Start editing. + + +# Locking +All kicad files are read-only by default, the file will need to be locked to your ssh key/gitlab account for it to be writable. +This can be done using `lock.sh {file name}`. +Once you are done editing the lock can be released using `unlock.sh {file name}`. + +Lock/unlock can only be done if there are any branches that aren't merged into `dev` (excluding `main`). + + +# CI +Edit lines 41 & 42 of .gitlab-ci.yml to match the naming/structure of your project/s. +You can add as many kicad projects as you like, as below: +``` + - DIR: 'proj1' + SCHEM: 'proj1.kicad_sch' + - DIR: 'proj2' + SCHEM: 'proj3.kicad_sch' + - DIR: 'proj3' + SCHEM: 'proj3.kicad_sch' +``` +The following will be produced on any commit to dev & main branches or any commit on branch that has an active MR with said branches: + - DRC & ERC + - Step files + + +The following will be produced only on commits to main or commits on dev if it has an active MR with main: + - JLCPCB compatible gerbers + - PDFs of Schematic & PCB + - BOM + + Currently there are some ERC errors to do with buses (https://gitlab.com/kicad/code/kicad/-/issues/13285), so the docker image used for CI will be run on an older version to avoid them. diff --git a/default.kibot.yaml b/default.kibot.yaml new file mode 100644 index 0000000..3618322 --- /dev/null +++ b/default.kibot.yaml @@ -0,0 +1,190 @@ +# Example KiPlot config file +kibot: + version: 1 +preflight: + run_erc: true + update_xml: true + run_drc: true + check_zone_fills: false + ignore_unconnected: false +global: + environment: + models_3d: "/models_3d" +outputs: + - name: 'print_sch' + comment: "Print schematic (PDF)" + type: pdf_sch_print + dir: . + options: + output: Schematic.pdf + + - name: 'print_front' + comment: "Print F.Cu+Dwgs.User" + type: pdf_pcb_print + dir: . + options: + output_name: PCB_Top.pdf + layers: + - layer: B.Cu + - layer: F.SilkS + + - name: 'bom' + comment: "BOM in csv format" + type: bom + dir: . + options: + columns: + - field: Value + name: Query + - field: Quantity Per PCB + name: Qty + - Description + - field: References + name: Schematic Reference + csv: + hide_pcb_info: true + hide_stats_info: true + format: "CSV" + + - name: 'drill' + comment: "excellon drill files" + type: excellon + dir: Gerbers + # options: + + - name: 'step' + comment: "Step file of pcb" + type: step + dir: . + options: + download: true + kicad_3d_url: https://gitlab.com/kicad/libraries/kicad-packages3D/-/raw/master/ + + - name: 'assembly' + comment: "Pick and place file, JLC style" + type: position + options: + output: '%f_cpl.%x' + format: CSV + units: millimeters + separate_files_for_front_and_back: false + only_smd: true + columns: + - id: Ref + name: Designator + - Val + - Package + - id: PosX + name: "Mid X" + - id: PosY + name: "Mid Y" + - id: Rot + name: Rotation + - id: Side + name: Layer + + - name: 'gerbers' + comment: "Gerbers for the board house" + type: gerber + dir: Gerbers + options: + # generic layer options + exclude_edge_layer: true + exclude_pads_from_silkscreen: false + use_aux_axis_as_origin: false + plot_sheet_reference: false + plot_footprint_refs: true + plot_footprint_values: true + force_plot_invisible_refs_vals: false + tent_vias: true + # gerber options + line_width: 0.1 + subtract_mask_from_silk: false + use_protel_extensions: false + gerber_precision: 4.6 + create_gerber_job_file: true + use_gerber_x2_attributes: true + use_gerber_net_attributes: true + layers: + - 'copper' + - 'technical' + - layer: Edge.Cuts + suffix: Edge_Cuts + + - name: JLCPCB_gerbers + comment: Gerbers compatible with JLCPCB + type: gerber + dir: JLCPCB + options: + exclude_edge_layer: true + exclude_pads_from_silkscreen: true + plot_sheet_reference: false + plot_footprint_refs: true + plot_footprint_values: false + force_plot_invisible_refs_vals: false + tent_vias: true + use_protel_extensions: true + create_gerber_job_file: false + disable_aperture_macros: true + gerber_precision: 4.6 + use_gerber_x2_attributes: false + use_gerber_net_attributes: false + line_width: 0.1 + subtract_mask_from_silk: true + inner_extension_pattern: '.g%n' + layers: + # Note: a more generic approach is to use 'copper' but then the filenames + # are slightly different. + - F.Cu + - B.Cu + - In1.Cu + - In2.Cu + - In3.Cu + - In4.Cu + - In5.Cu + - In6.Cu + - F.SilkS + - B.SilkS + - F.Mask + - B.Mask + - Edge.Cuts + + - name: JLCPCB_drill + comment: Drill files compatible with JLCPCB + type: excellon + dir: JLCPCB + options: + pth_and_npth_single_file: false + pth_id: '-PTH' + npth_id: '-NPTH' + metric_units: true + map: gerber + route_mode_for_oval_holes: false + output: "%f%i.%x" + + - name: JLCPCB_fab + comment: ZIP file for JLCPCB + type: compress + dir: JLCPCB + options: + files: + - from_output: JLCPCB_gerbers + dest: / + - from_output: JLCPCB_drill + dest: / + + - name: 'diff_pcb' + comment: "Diff for visual comparison" + type: diff + dir: . + options: + only_different: true + + - name: 'diff_sch' + comment: "Diff for visual comparison" + type: diff + dir: . + options: + only_different: true + pcb: false +