CI: set aux origin of each pcb to bottom left

This commit is contained in:
andrewc
2023-10-23 15:45:08 +10:00
parent 5f290a1b06
commit acd0758622
2 changed files with 17 additions and 0 deletions

15
.scripts/orig.py Normal file
View File

@@ -0,0 +1,15 @@
from kikit.common import resolveAnchor
from pcbnewTransition.pcbnew import LoadBoard,SaveBoard
import sys
from glob import glob
pcb_dir = sys.argv[1]
pcb_file = glob(pcb_dir + "/*.kicad_pcb")
board = LoadBoard(pcb_file[0])
bBox = board.GetBoardEdgesBoundingBox()
origin = resolveAnchor("bl")(bBox)
# print("origin: ", origin)
sett = board.GetDesignSettings()
sett.SetAuxOrigin(origin)
SaveBoard(pcb_file[0], board)

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@@ -61,8 +61,10 @@ image:
fi fi
echo ${dir_arr[i-1]} echo ${dir_arr[i-1]}
echo ${sch_arr[i-1]} echo ${sch_arr[i-1]}
python3 $CI_PROJECT_DIR/.gitlab/.scripts/orig.py ${dir_arr[i-1]}
cd ${dir_arr[i-1]} cd ${dir_arr[i-1]}
kibot -e ${sch_arr[i-1]} -c $CI_PROJECT_DIR/.gitlab/default.kibot.yaml -d $CI_PROJECT_DIR/Fabrication/${dir_arr[i-1]} -s $SUFFIX kibot -e ${sch_arr[i-1]} -c $CI_PROJECT_DIR/.gitlab/default.kibot.yaml -d $CI_PROJECT_DIR/Fabrication/${dir_arr[i-1]} -s $SUFFIX
cd $CI_PROJECT_DIR
done done
- cd $CI_PROJECT_DIR - cd $CI_PROJECT_DIR