Init

.gitignore

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+# For PCBs designed using KiCad: http://www.kicad-pcb.org/
+# Format documentation: http://kicad-pcb.org/help/file-formats/
+
+# Temporary files
+*.000
+*.bak
+*.bck
+*.kicad_pcb-bak
+*.kicad_sch-bak
+*.kicad_prl
+*.sch-bak
+*~
+_autosave-*
+**/#auto_saved_files#
+*.tmp
+*-save.pro
+*-save.kicad_pcb
+fp-info-cache
+
+# Netlist files (exported from Eeschema)
+*.net
+
+# Autorouter files (exported from Pcbnew)
+*.dsn
+*.ses
+
+# Exported BOM files
+*.xml
+*.csv
+
+# Backup Folders
+**/*backups/**
+
+# Log files
+*.log
+
+# CAD
+*.FCStd
+*.dxf

TODO.md

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+[ ] Readme
+[ ] Add micromelon kicad libaray as submodule
+[ ] Flesh out checklist
+[ ] Add kibot and CI yamls
+[ ] Update drawing templates with logo and sane values
+

checklist.md

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+# Design
+## Schematic
+| Status | Description | Notes |
+| ------ | ----------- | ----- | 
+| [] | 0R's on all regulator outputs and supply lines of critical ICs | | 
+| [] | Test points on all rails, comms, and complex/critical IO | | 
+| [] | Power budget | | 
+| [] | De-rating of capacitors and resistors | | 
+| [] | Voltage rating displayed for capacitors | Maybe move this to library checklist | 
+| [] | Thermal/current calculations for all regulators, switches, connectors, etc   | | 
+| [] |  | | 
+## PCB
+| Status | Description | Notes |
+| ------ | ----------- | ----- | 
+| [] |  | | 
+
+# Fabrication
+| Status | Description | Notes |
+| ------ | ----------- | ----- | 
+| [] | Ensure all branches merged in | | 
+| [] | Check number of layers | | 
+| [] |  | | 

proj.kicad_pcb

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+(kicad_pcb (version 20211014) (generator pcbnew)
+)

proj.kicad_pro

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+{
+  "board": {
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.1,
+        "copper_line_width": 0.2,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "other_line_width": 0.15,
+        "silk_line_width": 0.15,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "rules": {
+        "min_copper_edge_clearance": 0.0,
+        "solder_mask_clearance": 0.0,
+        "solder_mask_min_width": 0.0
+      },
+      "track_widths": [],
+      "via_dimensions": []
+    },
+    "layer_presets": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "proj.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12.0,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6.0
+      }
+    ],
+    "meta": {
+      "version": 2
+    },
+    "net_colors": null
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "legacy_lib_dir": "",
+    "legacy_lib_list": []
+  },
+  "sheets": [],
+  "text_variables": {}
+}

proj.kicad_sch

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+(kicad_sch (version 20211123) (generator eeschema)
+  (paper "A4")
+  (lib_symbols)
+  (symbol_instances)
+)