Fixed up where variant sits in output names, testing CI

This commit is contained in:
andrewc
2025-05-20 14:48:10 +10:00
parent 0f9ab507dd
commit 2663e63353
2 changed files with 14 additions and 11 deletions

View File

@@ -34,14 +34,14 @@ outputs:
type: pdf_sch_print type: pdf_sch_print
dir: . dir: .
options: options:
output: "%f%v_%r_%i.%x" output: "%f_%r%v_%i.%x"
- name: 'print_pcb' - name: 'print_pcb'
comment: "Print Top and Bottom Copper+Silk" comment: "Print Top and Bottom Copper+Silk"
type: pcb_print type: pcb_print
dir: . dir: .
options: options:
output: "%f%v_%r_PCB.%x" output: "%f_%r%v_PCB.%x"
pages: pages:
- layers: - layers:
- layer: F.Cu - layer: F.Cu
@@ -73,7 +73,7 @@ outputs:
- field: References - field: References
name: refs name: refs
exclude_filter: "" exclude_filter: ""
output: "%f%v_%r_%i.%x" output: "%f_%r%v_%i.%x"
expand_text_vars: true expand_text_vars: true
- name: 'bom_csv' - name: 'bom_csv'
@@ -112,7 +112,7 @@ outputs:
type: step type: step
dir: . dir: .
options: options:
output: '%f%v_%r.%x' output: '%f_%r%v.%x'
download: false download: false
subst_models: true subst_models: true
@@ -128,7 +128,7 @@ outputs:
download: false download: false
download_lcsc: false download_lcsc: false
orthographic: true orthographic: true
output: 'PCB_%f%v_%r.%x' output: 'PCB_%f_%r%v.%x'
show_components: 'none' show_components: 'none'
- name: 'pcba_render' - name: 'pcba_render'
@@ -143,14 +143,14 @@ outputs:
zoom: -1 zoom: -1
download_lcsc: false download_lcsc: false
orthographic: true orthographic: true
output: 'PCBA_%f%v_%r.%x' output: 'PCBA_%f_%r%v.%x'
show_components: 'all' show_components: 'all'
- name: 'neo_position' - name: 'neo_position'
comment: "Pick and place" comment: "Pick and place"
type: position type: position
options: options:
output: '%f%v_%r_cpl.%x' output: '%f_%r%v_cpl.%x'
format: CSV format: CSV
units: millimeters units: millimeters
separate_files_for_front_and_back: false separate_files_for_front_and_back: false
@@ -161,7 +161,7 @@ outputs:
type: stencil_3d type: stencil_3d
dir: '3D_Stencil' dir: '3D_Stencil'
options: options:
output: '%f%v_%r_%i.%x' output: '%f_%r%v_%i.%x'
- name: 'diff_pcb' - name: 'diff_pcb'
comment: "Diff for visual comparison" comment: "Diff for visual comparison"
@@ -185,7 +185,7 @@ outputs:
type: ibom type: ibom
dir: . dir: .
options: options:
output: '%f%v_%r_%i.%x' output: '%f_%r%v_%i.%x'
dark_mode: true dark_mode: true
- name: JLCPCB_gerbers - name: JLCPCB_gerbers
@@ -238,7 +238,7 @@ outputs:
metric_units: true metric_units: true
map: gerber map: gerber
route_mode_for_oval_holes: false route_mode_for_oval_holes: false
output: "%f%v%i.%x" output: "%f_%r%v_%i.%x"
- name: 'JLCPCB_compress' - name: 'JLCPCB_compress'
comment: ZIP file for JLCPCB comment: ZIP file for JLCPCB
@@ -249,7 +249,7 @@ outputs:
dest: / dest: /
- from_output: JLCPCB_drill - from_output: JLCPCB_drill
dest: / dest: /
output: '%f%v_%r_JLC.%x' output: '%f_%r%v_JLC.%x'
# groups: # groups:
# - name: pcb # - name: pcb
# outputs: # outputs:

View File

@@ -160,6 +160,7 @@ image:
name=$(echo $f | cut -c3- | cut -d'-' -f1)A name=$(echo $f | cut -c3- | cut -d'-' -f1)A
fab_path=$CI_PROJECT_DIR/Fabrication/$(dirname $f | cut -c3-) fab_path=$CI_PROJECT_DIR/Fabrication/$(dirname $f | cut -c3-)
name_n_rev=$(echo $f | cut -c3- | rev | cut -d'/' -f1 | cut -c9- | rev) name_n_rev=$(echo $f | cut -c3- | rev | cut -d'/' -f1 | cut -c9- | rev)
echo "name: $name_n_rev"
pcb_im=$fab_path/PCB_$name_n_rev.png pcb_im=$fab_path/PCB_$name_n_rev.png
pcba_im=$fab_path/PCBA_$name_n_rev.png pcba_im=$fab_path/PCBA_$name_n_rev.png
pcb_attach=$(echo "['$fab_path/${name_n_rev}_PCB.pdf', '$CI_PROJECT_DIR/Fabrication/${name_n_rev}_JLC.zip']") pcb_attach=$(echo "['$fab_path/${name_n_rev}_PCB.pdf', '$CI_PROJECT_DIR/Fabrication/${name_n_rev}_JLC.zip']")
@@ -265,6 +266,8 @@ outputs_dev:
outputs_main: outputs_main:
extends: outputs_dev extends: outputs_dev
rules:
- !reference [.main_rules, rules]
script: script:
# SCH # SCH
- VARIANTS="$VARIANTS_SCH" - VARIANTS="$VARIANTS_SCH"